Cadence SPB OrCAD 16.50.007 - 16.50.010
Cadence SPB OrCAD 16.50.007 - 16.50.010 | 1.81 GB
Single Extraction - InterChangable - No Password
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
Company Profile:
To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.
Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.
New Allegro 16.5 Technology:
The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB
designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations
Fixed in Cadence SPB OrCAD 16.5.010:
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
941499 ALLEGRO_EDITOR DRAFTING BUG:Limit Tolerance isnot working for Dimensioning
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
942914 SIG_INTEGRITY OTHER ZAxis delay calculation
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
946819 SIP_LAYOUT DEGASSING Shape degass command
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
DATE: 10-26-2011 HOTFIX VERSION: 009
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
DATE: 10-21-2011 HOTFIX VERSION: 008
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
929348 F2B BOM Warning 007: Invalid output file path name
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
930783 CONCEPT_HDL CORE Painting with groups with default colors
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows “?” on lower hierarchy level nets after Upreving to 16.5 version.
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
942210 SCM OTHER Is the Project File argument is being correctly passed?
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
DATE: 10-07-2011 HOTFIX VERSION: 007
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
841096 APD WIREBOND Function required which to check wire not in die pad center.
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
906692 ADW LRM LRM window is always in front when opening a project
912942 APD WIREBOND constraint driven wire bonding
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
932292 ADW LRM LRM crashes during Update operation on a customer design
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
932871 APD GRAPHICS could not see cursor as infinite
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
933214 APD ARTWORK Film area report is larger when fillets are removed
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
934909 SCM UI Require support for running script on loading a design in SCM
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
I will check, If link dead, I will reupload at here
Code:
http://tinypaste.com/832cc84c
Download Filesonic
Code:
http://www.filesonic.com/file/3894696345/Hotfix_SPB16.50.part1.rar
http://www.filesonic.com/file/3894696445/Hotfix_SPB16.50.part2.rar
http://www.filesonic.com/file/3894696515/Hotfix_SPB16.50.part3.rar
http://www.filesonic.com/file/3894696635/Hotfix_SPB16.50.part4.rar
http://www.filesonic.com/file/3894695995/Hotfix_SPB16.50.part5.rar
(Sưu tầm và chia sẻ bởi Sinhvienthamdinh.Com)
Cadence SPB OrCAD 16.50.007 - 16.50.010 | 1.81 GB
Single Extraction - InterChangable - No Password
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
Company Profile:
To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.
Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.
New Allegro 16.5 Technology:
The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB
designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations
Fixed in Cadence SPB OrCAD 16.5.010:
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
941499 ALLEGRO_EDITOR DRAFTING BUG:Limit Tolerance isnot working for Dimensioning
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
942914 SIG_INTEGRITY OTHER ZAxis delay calculation
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
946819 SIP_LAYOUT DEGASSING Shape degass command
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
DATE: 10-26-2011 HOTFIX VERSION: 009
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
DATE: 10-21-2011 HOTFIX VERSION: 008
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
929348 F2B BOM Warning 007: Invalid output file path name
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
930783 CONCEPT_HDL CORE Painting with groups with default colors
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows “?” on lower hierarchy level nets after Upreving to 16.5 version.
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
942210 SCM OTHER Is the Project File argument is being correctly passed?
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
DATE: 10-07-2011 HOTFIX VERSION: 007
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
841096 APD WIREBOND Function required which to check wire not in die pad center.
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
906692 ADW LRM LRM window is always in front when opening a project
912942 APD WIREBOND constraint driven wire bonding
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
932292 ADW LRM LRM crashes during Update operation on a customer design
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
932871 APD GRAPHICS could not see cursor as infinite
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
933214 APD ARTWORK Film area report is larger when fillets are removed
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
934909 SCM UI Require support for running script on loading a design in SCM
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
I will check, If link dead, I will reupload at here
Code:
http://tinypaste.com/832cc84c
Download Filesonic
Code:
http://www.filesonic.com/file/3894696345/Hotfix_SPB16.50.part1.rar
http://www.filesonic.com/file/3894696445/Hotfix_SPB16.50.part2.rar
http://www.filesonic.com/file/3894696515/Hotfix_SPB16.50.part3.rar
http://www.filesonic.com/file/3894696635/Hotfix_SPB16.50.part4.rar
http://www.filesonic.com/file/3894695995/Hotfix_SPB16.50.part5.rar
(Sưu tầm và chia sẻ bởi Sinhvienthamdinh.Com)
